1. Field of the Invention
The present invention relates generally to a data processing system and more specifically to a method, computer program product and system for analyzing and reducing byte movement operations in SIMD code.
2. Description of the Related Art
Modern processors use Single Issue Multiple Data (SIMD) units to significantly increase the processing throughputs without having to increase their issue bandwidth. Since multiple data can be processed in one computation, SIMD architecture often provides various data reordering operations, to organize the data into the desired location of the wide register prior to processing.
Currently, solutions exist that minimize the data reordering operations introduced exclusively for realignment purposes. However, none of these solutions is capable of handling other types of data reordering operations nor do the solutions address combining different data reordering operations to reduce the number of data reordering operations present in SIMD code.
For SIMD architectures such as Vector/SIMD Multimedia extension (VMX) or Synergistic Processing Unit (SPU), only loads and stores from vector length aligned memory addresses are supported. Such architectures are referred to as SIMD architectures with alignment constraints. For SIMD architectures with alignment constraints, a valid “SIMDization” may introduce a data reorganization operation per misaligned loads and stores. “SIMDization” is vectorization for SIMD architectures. Thus, alignment handling is a common cause of implicit data reordering operations (discussed further below) present in SIMD code.